Crosstalk between adjacent clock signal generators can cause noise and/or other effects within a frequency band of interest. For example, crosstalk between oscillators in different PLLs may produce noise in clock signals generated by those PLLs. In order to meet performance specifications in SONET (Synchronous Optical Network), OTN (Optical Transport Network), and other types of communication systems, very low bandwidth cleanup PLLs might be preferred to remove noise from recovered or mapped/demapped clock signals. However, such low bandwidth cleanup PLLs can exhibit poor crosstalk immunity. Wider bandwidth might reduce crosstalk, but at the cost of reduced reference noise filtering and such effects as clock signal jitter.
Consider an illustrative example of a jitter transfer specification having a 300 Hz pole. An actual implementation that satisfies such a specification might require a filter or filtering function with a 100 Hz pole. This would not be feasible for integrated analog filters, for instance, in many applications due to the large size of the capacitors in such filters. Other implementations might include very clean but costly VCXOs (Voltage Controlled Crystal Oscillators), or stand-alone cleanup PLLs. Although stand-alone PLLs could be displaced from each other to reduce crosstalk, the cost associated with providing external cleanup PLLs tends to be much greater than the cost of integrating multiple PLLs on the same chip or board or in the same package as other components. Providing space between PLLs also consumes “real estate”, which could be limited in a chip, in a package, or on a board, especially in applications that include multiple cleanup PLLs. A PLL with a conventional integrated VCO (Voltage Controlled Oscillator) needs a wide bandwidth to suppress the noise of the VCO. Without this wide bandwidth, low noise requirements placed on the VCO would require it to draw excessive power, to the point of being unrealizable.